The present invention relates to complimentary metal oxide semiconductor (CMOS) phase rotators.
CMOS phase rotators are used in serial link receivers to adjust the phase of a sampling clock. Typical phase rotators include three stages: (a) a phase selector stage that receives a clock signal consisting of multiple phases from a clock generator and selects from that multiphase clock signal two phases that are interpolated; (b) a strength control (slew rate control) stage that adjusts the slew rate of the two phase signals selected to improve the linearity in the successive phase interpolation; and (c) a weight control (phase blending) stage that performs phase blending and outputs a phase-rotated signal.
Previous CMOS phase rotators include a strength control stage having a plurality of field effect transistors (FETs) arranged as current-starved inverters. The number of FETs used in the arrangement is determined by the strength of the slew rate. The slew rate represents the rate of change of the selected phase signals, and is a measure for the steepness of the signal edges. Slew rate is measured in volts per second (V/s). If the signal edges are too steep (which corresponds to too high a value of the slew rate), the phase interpolation in the successive phase blending stage becomes undesirably nonlinear and may lead to unequal or even non-monotonic phase steps. The drive strength control stage reduces the slew rate of the selected phase signals. There is an optimum value in the slew rate reduction since too low a value of the slew rate increases timing jitter and may prevent the signal from remaining full swing. At lower frequencies, the typical slew rate strength is greater than at higher frequencies because of the smaller impact of parasitic capacitances at lower frequencies that do not sufficiently load the signals. As a consequence, the current starving in the current starved inverters is increased, which results in a greater number of stacked FETs. However, if the frequency is very high, the impact of the capacitive parasitics becomes stronger, and the signals may not reach full-swing. In such a case, additional current-starved inverters are switched in parallel to increase the drive strength, which also increases the slew rate to the optimum value. A greater number of FETs are required in the arrangement if the bandwidth of the CMOS phase rotator is increased either towards higher or lower frequencies. These FETs in the additional current starved inverter stages, and the control lines used to operate the FETs occupy valuable space in a CMOS device and consume power.
As CMOS devices become smaller, it is desirable to reduce the amount of space to increase the integration density and the power used by FETs in the devices to become more energy-efficient.